1. Field of the Invention
The present invention relates to a digital synchronous circuit for providing an output clock signal synchronized in phase with an input data signal from outside.
2. Description of the Background Art
One technique of implementing a synchronous circuit for providing an output clock signal synchronized with the phase of an input data signal sent serially from outside the chip is described in B. Kim, D. N. Helman, and P. Gray, “A 30-MHz Hybrid Analog/Digital Clock Recovery Circuit in 2 μm CMOS,” J.S.S.C. (Journal of Solid-State Circuits,) 1990 Vol. 25, No. 6, pp. 1385–1394.
In this technique, a method of generating and utilizing multiphase clock signals by voltage controlled oscillator (hereinafter referred to as VCO) formed by a group of inverters connected in a loop and whose delay time can be controlled is devised.
A multiphase clock generating circuit for generating the multiphase clock has a PLL (Phase Lock Loop) configuration in which the oscillation frequency of VCO is controlled to be the same as the frequency of an input data signal input from outside the chip. In this configuration, multiphase clock signals, i.e. a plurality of clock signals having the same frequency, a constant phase difference, and different phases, are output by taking out the signals from each node of the group of inverters connected in a loop within VCO.
FIG. 8 is a block diagram of the configuration of a conventional digital synchronous circuit using multiphase clock signals.
A conventional digital synchronous circuit is formed by a multiphase clock generating circuit 10 for outputting n clock signals CLK1 to CLKn, latch circuits 20 and 30 each of n bits, a clock phase determination circuit 50, a selector 60 for selecting and outputting one clock signal from n clock signals CLK1 to CLKn.
In addition, latch circuit 20 of n bits is formed by n D-type flip-flops FF1 to FFn.
Now, the connections of the conventional digital synchronous circuit will be described.
Clock signals CLK1, CLK2, . . . , CLKn output from multiphase clock generating circuit 10 are applied respectively to the clock input terminals of flip-flops FF1, FF2, . . . , FFn within latch circuit 20 and respectively to a first data input terminal, a second data input terminal, . . . , and an n-th data input terminal of selector 60. An input data signal DIN is provided to all data input terminals of flip-flops FF1 to FFn.
Moreover, output signals of flip-flops FF1, FF2, . . . , FFn are respectively applied to a first-bit data input terminal, a second-bit data input terminal, . . . , and an n-th bit data input terminal of latch circuit 30 of n bits. A clock input terminal of latch circuit 30 of n bits is provided with a clock signal CLKn.
The output signals of n bits from latch circuit 30 are applied to input terminals of clock phase determination circuit 50.
Further, a clock selecting signal CSL output from clock phase determination circuit 50 is provided to a control input terminal of selector 60, and an output clock signal OUTCLK is output from an output terminal of selector 60.
Now, the operation of the conventional digital synchronous circuit will be described.
Multiphase clock generating circuit 10 outputs clock signals CLK1 to CLKn each having the same frequency as input data signal DIN and each having different phases.
Input data signal DIN is latched by flip-flops FF1, FF2, . . . , FFn within latch circuit 20 respectively according to clock signals CLK1 to CLKn output from multiphase clock generating circuit 10. Thus, input data signal DIN is sampled by clock signals CLK1 to CLKn, and the sampled data is held in flip-flops FF1 to FFn.
The sampled data held in flip-flops FF1 to FFn are taken into latch circuit 30 forming the next stage by clock signal CLKn.
Then, n bits of data held in latch circuit 30 are provided to clock phase determination circuit 50.
Here, clock phase determination circuit 50 determines the state of the change in the potential level of the signal obtained by sampling input data signal DIN in time sequence to output clock selecting signal CSL for selecting one of clock signals CLK1 to CLKn as the most suitable clock signal for correctly sampling input data DIN.
Selector 60 selects one of clock signals CLK1 to CLKn based on the value of clock selecting signal CSL, and outputs the selected signal as output clock signal OUTCLK.
As described above, one of clock signals CLK1 to CLKn having a phase synchronized with input data signal DIN is selected and the selected signal is output as output clock signal OUTCLK. Thus, a synchronous circuit that operates by digital control is implemented.
Here, the problem of meta-stable phenomenon arises where the outputs of flip-flops FF1 to FFn within latch circuit 20 become temporarily unstable under certain conditions.
The meta-stable phenomenon occurs when the point of change in the potential of input data signal DIN input to flip-flops FF1 to FFn and a point of change in the potential of clock signals CLK1 to CLKn provided to the clock input terminals of flip-flops FF1 to FFn coincide in time.
When the meta-stable phenomenon occurs, the potential of an output of a flip-flop which is the sampling result of input data signal DIN temporarily becomes intermediate, that is, neither at the logic high (“H”) level nor at the logic low (“L”) level, and thus unstable.
If an output from this flip-flop is taken into latch circuit 30 before the unstable state of the potential settles to either the “H” level or the “L” level, there is a possibility that the potential of an output from latch circuit 30 also becomes intermediate or neither at the “H” level nor at the “L” level due to the meta-stable phenomenon, causing the potential level to be temporarily indefinite.
Thus, the occurrence of the meta-stable phenomenon in flip-flops FF1 to FFn adversely affects the operation of a circuit that receives the signal having the intermediate potential, thereby making it difficult to output the output clock signal OUTCLK, which is an output of the digital synchronous circuit, in a normal manner.
To avoid such an indefinite state of data, such measures are contemplated as forming latch circuit 30 by flip-flop circuits each having a master-slave construction or connecting such flip-flop circuits in multiple stages to gain enough time for the meta-stable state to be resolved.
Implementing such flip-flop circuits each with a master-slave construction or the multiple-stage connection thereof to gain time, however, increases the circuit scale, creating disadvantages with respect to the chip area and power consumption.
Moreover, when such flip-flop circuits each with a master-slave construction or the multiple-stage connection thereof is implemented, the circuit scale of the corresponding portion would be proportionate to n. Thus, the greater the value of n is, the greater the disadvantages become with respect to the chip area and power consumption.